Note that this cheat sheet omits some corner cases and other technical details in favor of understandability. It is also not even close to being a complete listing of the x86 instruction set. For an easy-to-use but thorough reference, see https://www.felixcloutier.com/x86/
x86 has a small set of registers with specific meanings:
All the most valuable content has already been moved: the bulk of the x86 instruction examples with assertions. There is some stuff left here, e.g. 32-bit x86 and some useless prose. Maybe one day I'll migrate them, let's see. No major new features are intended to be added here. Notable advantages. X86-cheat-sheet-day7 Author: Remzi Arpaci-Dusseau Created Date: 3/2/2017 7:22:35 PM. X8664 cheat sheet? The documentation of fasm may not answer such questions, because it generally aims to define syntax, with focus on the details that may differ from the x86 dialects of other assemblers. X86-64 (also known as just x64 and/or AMD64) is the 64-bit version of the x86/IA32 instruction set. Below is our overview of its features that are relevant to CS107. There is more extensive coverage on these topics in Chapter 3 of the B&O textbook. See also our x86-64 sheet for a compact reference.
|stores a pointer to the next instruction.|
|points to the top of the call stack.|
|points to the bottom of the call stack.|
|is general purpose, but is also used to return values from functions.|
|stores processor flags.|
|are general purpose registers unless otherwise noted.|
TR x86 Assembly Cheat Sheet. CanYouPwnMe Mart 18, 2016 Cheat Sheet 1 Comment 2234 views. A scene from matrix “There’s way too much information to decode the Matrix. You get used to it, though. Your brain does the translating. I don’t even see the code.
add <dst>, <src>: adds two operands.
<src>to the value in
<dst>and store in
- Set the overflow (
OF), carry (
CF), and sign (
SF) bits in the
eflagsregister as appropriate.
call <label>: executes the function at
eipin location pointed to by
- Jump to location specified by operand.
cmp <dst>, <src>: compare two values.
- Set zero flag (
ZF) and carry (
CF) according to table:
je <dst>: jump if equal, also known as the Jay-Z instruction,
- In the
<dst>, otherwise advance
jmp <dst>: unconditional jump (alters
lea <dst>, <src>: “load effective address”; often used to dereference fields in a struct.
- Compute address expression in
<src>, store in
leave: function teardown shortcut.
- Copy value pointed to by
mov <dst>, <src>: copies a value from the
<src> memory location to the
<dst> memory location.
- Store the value in the second operand into the location in the first operand.
nop: do nothing for one cycle.
pop <dst>: removes a value from the stack and puts it in
- Store value pointed to by
espinto operand register.
push <src>: puts the value in
<src> on the stack.
- Store operand in location pointed to by
ret: returns to stack-saved address (does not advance
- Copy value at the location pointed to by
sub <dst>, <src>: subtracts two operands.
<dst>and store in
- Set the overflow (
OF), carry (
CF), and sign (
SF) bits in
This reference is intended to be precise opcode and instruction set reference (including x86-64). Its principal aim is exact definition of instruction parameters and attributes.
coder32, coder32-abc, geek32, geek32-abc
coder64, coder64-abc, geek64, geek64-abc
coder, coder-abc, geek, geek-abc (these contain both x86-32 and x64 instructions).
In contrast to other references, primary source of this reference is an XML document, which guarantees clear and structured information base and therefore ability to extract many various informations such as a list of instructions from requested groups, etc.
The reference is primarily based on Intel manuals as Intel is the originator of x86 architecture. Additionally, it describes undocumented instructions as well. On appropriate places, it gives a notice if an opcode act differently on AMD architecture. Support for Cyrix, NexGen etc. specific instructions is not scheduled at all.
These editions are available at the moment: The coder suite is intended to more common use and contains the following editions: coder32, coder64, and coder (sorted by opcode), and coder32-abc, coder64-abc, and coder-abc (sorted by mnemonic). The geek suite is intended for deeper research of x86 architectures' instruction set. This includes geek32, geek64, and geek editions (by opcode) and geek32-abc, geek64-abc, and geek-abc editions (by mnemonic). More on the purpose and use of this suite see close below.
Don't get confused by geek(-abc) and coder(-abc) editions. Both of them contains instruction set of both x86-32 and x86-64 architectures. If you don't have a particular reason to use them (such as to view the differencies between the architectures), the other editions would probably suit you better.
Editions coder32 a geek32 relate exclusively to x86-32 architecture. Similarly, editions coder64 and geek64 relate exclusively to x86-64 architecture.
The following chart illustrates the differencies between editions for current release:
|Supported Architectures||both||pure x86-32||pure x86-64||both||pure x86-32||pure x86-64|
|Opcode Bitfields Information||no||no||no||yes||yes||yes|
|Instruction Extension Indicated||yes||yes||yes||yes||yes||yes|
|Instruction Group Indicated||no||no||no||yes||yes||yes|
|Intel SSE (all)||yes||yes||yes||yes||yes||yes|
The Purpose of Geek Editions in Short
The geek editions contains as much complete information from the source XML document as possible. That's why they may seem quite unclear. You appreciate them only if you need to get to know the instruction set deeply or if you investigate the source XML and you need to visualize it better.
These editions use specific operand codes (which are described in Instruction Operand Codes chapter below). These codes may look strange and obscure at the first sight. The reason to use them is that they hold more information than the more common ones. One example can be operand combination
rAX, imm16/32, such as in instruction
ADD rAX, imm16/32 in coder64 edition. One can determine that the destination operand is either
rax, and the source one is either
imm32. A problem arises when one needs to determine what magic is behind
rax, imm32 combination. If one is just getting started with x64 architecture, it is not clear how exactly is 32-bit immediate added to 64-bit
rax. This question is answered by corresponding geek edition,
ADD rAX, Ivds in geek64 edition. The immediate value is encoded there using
I code means Immediate,
v means word or doubleword (
imm32). The most important part is
ds code, which means doubleword, sign-extended to 64 bits for 64-bit operand size. Now is it clear.
As for Itanium-specific instructions, they are added just for the sake of interest - they give a notice that the appropriate opcodes are already used.
Hypertext Reference to Particular Opcode
If you want to refer to particular opcode (in any edition), e. g.,
0FA0 PUSH FS, it can be easily achieved this way:
ref.x86asm.net/geek.html#x0FA0 (try it)
It works for opcode extension similarly, e. g.,
83 /7 CMP:
ref.x86asm.net/coder32.html#x83_7 (try it)
Using HTML Editions
Since HTML editions can look complicated at first sight, here goes an outline how to work with them. Following examples come from coder32's edition because it is easier to use than geek's editions.
Example: ADC Instruction
Let's start with more known instruction, such as
ADC. We find something similar to the following:
First column pf (Prefix) is empty. That means the instruction's opcode doesn't contain any fixed prefix.
Next column 0F is just allocated for
0F prefix for multiple-byte opcodes so it is empty.
Next column po (Primary Opcode) holds primary opcode value itself.
Because the instruction's opcode doesn't contain any added byte, the column so (Secondary Opcode) is empty too.
The opcode doesn't contain any specific bits so the column flds (Opcode Fields) is empty.
The column o (Register/Opcode Field) here holds 'r', which indicates that the instruction uses 'full' ModR/M byte (no opcode extension).
Because this instruction is supported since 8086 processor, proc column (Introduced with Processor) is empty.
This instruction is officially documented so st column is empty too.
ADC can work on any ring level so the column rl, Ring Level, is empty.
The column x holds 'L', which means that
LOCK prefix is allowed with this instruction.
Next three columns, mnemonic, op1 and op2 show instruction's syntax. The destination operand of this instruction is set up using bold, what always means the operand is modified by the instruction.
The column iext (Instruction Extension Group) is empty because the instruction doesn't belong to any instruction set extension.
Columns grp1 and grp2 classify the instruction among general arithmetic instructions.
ADC instruction is influenced by CF flag, what represents tested f column.
This instruction influences (overwrites) all status flags. These can be found in next column modif f column.
All of these flags are defined (don't contain random values) so the same flags are in next def f column, and undef f column must be empty.
No flag is set to a fixed value (all modified flags depend on input operands) so f values column is empty.
Last column description, notes contains only a general description of the instruction.
Example: Opcode Extensions
Some opcodes (only a few) depend on Opcode Extension Field in ModR/M byte. Using this field, the opcode is actually extended by three bits. In most cases, different extension of the same opcode means more or less different instruction. An example can be opcode
F6. We choose last three extensions of the opcode:
The opcode extension can be a value from 0 through 7. These values are indicated in o (Register/Opcode Field) column. In this example, values 5, 6, and 7 are chosen.
Additionally, this example shows that operands, which are not explicitly used (
AX operands), are set up using italic. It also shows that
IDIV instructions always destroy all status flags: both modif f and undef f column contain these flags.
Example: One Opcode, More Syntaxes
Some opcodes are represented by more instructions with the same meaning, using different syntaxes. (This doesn't apply to the case when an opcode depends on Opcode Extension field in ModR/M byte. In this case, these instructions act more or less differently). Best known example are conditional jumps, for example
JZ/JE, where we find something similar:
Each syntax has dedicated row in mnemonic column and in columns with instruction operands.
More complex case is, for example,
Here, the opcode's record is complicated by the fact that since 80386 processor, the syntax is extended (thanks to 32-bit operands) with
MOVSD mnemonic and
MOVS syntax is changed. That's why all four syntaxes have to be split by twos.
More examples with multiple syntaxes:
Example: Undocumented Instruction SETALC
All main editions contain a few undocumented instructions (from the Intel manual point of view). No that in this reference, undocumented doesn't equal invalid. All undocumented instructions mentioned by this reference work well in their shape. It is, for example,
In this case, the documented meaning goes first, as indicated in st column by 'D' value. Since this opcode's documented meaning is not a common one, there is additional reference to the description where the opcode is documented. The column mnemonic implies by the value 'undefined' (which is set up using italic, which always means here that it is not an original mnemonic) that the documented meaning of this opcode is 'undefined and reserved'. This is also stated in the last column.
Below goes the undocumented meaning of the opcode - st column holds 'U' value. Each undocumented meaning should contain a reference to the description where is the opcode unofficially documented, like in this case.
More examples of undocumented instructions:
- pf Prefix
- po Primary Opcode
- so Secondary Opcode
- flds Opcode Fields
- o Register/Opcode Field
- proc Introduced with Processor
- st Documentation Status
- m Mode of Operation
- rl Ring Level
- x Lock Prefix/FPU Push/FPU Pop
- mnemonic Instruction Mnemonic
- op1, op2, … Instruction Operands
- iext Instruction Extension Group
- grp1, grp2, grp3 Main Group, Sub-group, Sub-sub-group
- tested f, modif f, def f, undef f Tested, Modified, Defined, and Undefined Flags
- f values Flags Values
|pf||Prefix||Fixed extraordinary prefix, which may change the semantic of the Primary Opcode. Usually used in case of waiting x87 FPU instructions, and many SSE instructions. |
|Dedicated for |
|po||Primary Opcode||Basic opcode. Second opcode byte in case of two- and three-byte opcodes. For coder's editions: |
|so||Secondary Opcode||Fixed appended value to the primary opcode. It is used in some special cases, x87 FPU instructions and for new three-byte instructions. |
|flds||Opcode Fields||This column is present only in geek's editions. It contain present Primary Opcode binary fields. These are: |
|o||Register/ Opcode Field|
|proc||Introduced with Processor||Indicates the instruction's introductory processor (code in curves apply to XML reference): |
|st||Document. Status||Indicates how is the instruction documented in the Intel manuals: |
|m||Mode of Operation||Indicates the mode, which is the instruction valid on. Virtual-8086 Mode is not taken into account. |
|rl||Ring Level||The ring level, which is the instruction valid (3 or 0) from; |
|FPU Push/ FPU Pop||The following codes apply only to x87 FPU instructions (none of them can use |
|mnemonic||Instr. Mnemonic||The instruction mnemonic itself. If there is no mnemonic, it holds additional information about the mnemonic or instruction: |
|Only geek's editions: |
|op1, op2, ...||Instr. Operands||Instruction operands. Geek's editions use special operand codes, explained in Instruction Operand Codes chapter below. If an operand is set up using italic, it is an implicit operand, which is not explicitly used. If an operand is set up using boldface, it is modified by the instruction.|
|iext||Instr. Extension Group||The instruction extension group, which was the opcode released on: |
|grp1, grp2, grp3||Main Group, Sub-group, Sub -sub-group||These columns are present only in geek's editions. They classifies the instruction among groups. These groups don't match the instruction groups given by the Intel manual (I found them too loose). One instruction may fit into more groups. |
|tested f, modif f, def f, undef f||Tested, Modified, Defined, and Undefined Flags|
|f values||Flags Values|
|description, notes||Short desciption of the opcode. For now, the descriptions are very general. They will be improved in future perhaps.|
Instruction Operand Codes
These codes come from official codes used in Intel manual Instruction Set Reference, N-Z for Pentium 4 processor, revision 17. The reason of using this particular, out-of-date revision is that the codes from this revision are most apposite ones. In next revisions the codes changed unfortunately. These codes were modified and completed mainly because of the possibility to code operands simultaneously for 64-bit mode. Ideally, it would be the best to make brand new codes, but I'm afraid those wouldn't be widely acceptable.
The State column says if the code is original, added or changed.
The 'Geek' part in these tables in the first column indicates codes used in HTML geek's editions and in the source XML document as well. The 'Coder' part indicates alternative codes used in HTML coder's editions. These are used also within instruction reference in Intel manual.
Codes for Addressing MethodThe following abbreviations are used for addressing methods:
|Original||Direct address. The instruction has no ModR/M byte; the address of the operand is encodedin the instruction; no base register, index register, or scaling factor can be applied(for example, far |
|Added||Memory addressed by |
|Added||Memory addressed by |
|Added||Memory addressed by |
|Original||The reg field of the ModR/M byte selects a control register (only |
|Original||The reg field of the ModR/M byte selects a debug register (only |
|Original||A ModR/M byte follows the opcode and specifies the operand. The operand is either a general-purpose register or a memory address. If it is a memory address, the address is computed from a segment register and any of the following values: a base register, an index register, a scaling factor, or a displacement.|
|Added||(Implies original |
|Added||(Implies original |
|Original||The reg field of the ModR/M byte selects a general register (for example, |
|Added||The r/m field of the ModR/M byte always selects a general register, regardless of the mod field (for example, |
|Original||Immediate data. The operand value is encoded in subsequent bytes of the instruction.|
|Original||The instruction contains a relative offset to be added to the instruction pointer register(for example, |
|Original||The ModR/M byte may refer only to memory: mod != 11bin (|
|Original||The R/M field of the ModR/M byte selects a packed quadword MMX technology register.|
|Original||The instruction has no ModR/M byte; the offset of the operand is coded as a word, double word or quad word (depending on address size attribute) in the instruction. No base register, index register, or scaling factor can be applied (only |
|Original||The reg field of the ModR/M byte selects a packed quadword MMX technology register.|
|Original||A ModR/M byte follows the opcode and specifies the operand. The operand is eitheran MMX technology register or a memory address. If it is a memory address, the addressis computed from a segment register and any of the following values: a base register,an index register, a scaling factor, and a displacement.|
|Original||The mod field of the ModR/M byte may refer only to a general register (only|
|Original||The reg field of the ModR/M byte selects a segment register (only |
|Added||Stack operand, used by instructions which either push an operand to the stack or pop an operand from the stack. Pop-like instructions are, for example, |
|Original||The reg field of the ModR/M byte selects a test register (only |
|Original||The R/M field of the ModR/M byte selects a 128-bit XMM register.|
|Original||The reg field of the ModR/M byte selects a 128-bit XMM register.|
|Original||A ModR/M byte follows the opcode and specifies the operand. The operand is either a128-bit XMM register or a memory address. If it is a memory address, the address iscomputed from a segment register and any of the following values: a base register, anindex register, a scaling factor, and a displacement|
|Original||Memory addressed by the |
|Original||Memory addressed by the |
|Added||The instruction has no ModR/M byte; the three least-significant bits of the opcode byte selects a general-purpose register|
At&t Assembly Cheat Sheetaddress atribute of syntax/dst or syntax/src elements. All of them are added:
|The two bits at bit index three of the opcode byte selects one of original four segment registers (for example, |
|The three least-significant bits of the opcode byte selects segment register |
|The three bits at bit index three of the opcode byte selects segment register |
Codes for Operand TypeThe following abbreviations are used for operand types:
|Original||Two one-word operands in memory or two double-word operands in memory, dependingon operand-size attribute (only |
|Original||Byte, regardless of operand-size attribute.|
|Added||Packed-BCD. Only x87 FPU instructions (for example, |
|Added; simplified ||Byte, sign-extended to the size of the destination operand.|
|Original; replaced by ||(Byte, sign-extended to 64 bits.)|
|Original||Byte, sign-extended to the size of the stack pointer (for example, |
|Original||Byte or word, depending on operand-size attribute. (unused even by Intel?)|
|Original||Doubleword, regardless of operand-size attribute.|
|Added||Doubleword-integer. Only x87 FPU instructions (for example, |
|Original||Double-quadword, regardless of operand-size attribute (for example, |
|Added; combines ||Doubleword, or quadword, promoted by |
|Added||Double-real. Only x87 FPU instructions (for example, |
|Original||Doubleword, sign-extended to 64 bits (for example, |
|Added||x87 FPU environment (for example, |
|Added||Extended-real. Only x87 FPU instructions (for example, |
|Original||32-bit or 48-bit pointer, depending on operand-size attribute (for example, |
|Original||Quadword MMX technology data.|
|Original||128-bit packed double-precision floating-point data.|
|Original||128-bit packed single-precision floating-point data.|
|Added||64-bit packed single-precision floating-point data.|
|Original; replaced by ||(80-bit far pointer.)|
|Added||32-bit or 48-bit pointer, depending on operand-size attribute, or 80-bit far pointer, promoted by |
|Original||Quadword, regardless of operand-size attribute (for example, |
|Added||Qword-integer. Only x87 FPU instructions (for example, |
|Original||Quadword, promoted by |
|Changed to||6-byte pseudo-descriptor, or 10-byte pseudo-descriptor in 64-bit mode (for example, |
|-||Changed from||6-byte pseudo-descriptor.|
|Original||Scalar element of a 128-bit packed double-precision floating data.|
|Original||Doubleword integer register (e. g., |
|Added||Single-real. Only x87 FPU instructions (for example, |
|Original||Scalar element of a 128-bit packed single-precision floating data.|
|Added||x87 FPU state (for example, |
|Added||x87 FPU and SIMD state (|
|Original; replaced by ||10-byte far pointer.|
|Original||Word or doubleword, depending on operand-size attribute (for example, |
|Added; combines ||Word or doubleword, depending on operand-size attribute, or doubleword, sign-extended to 64 bits for 64-bit operand size.|
|Original||Quadword (default) or word if operand-size prefix is used (for example, |
|Added; combines ||Word or doubleword, depending on operand-size attribute, or quadword, promoted by |
|Original||Word or doubleword sign extended to the size of the stack pointer (for example, |
|Original||Word, regardless of operand-size attribute (for example, |
|Added||Word-integer. Only x87 FPU instructions (for example, |
|Word or doubleword, according to address-size attribute (only |
|Doubleword or quadword, according to address-size attribute (only |
|Word, according to address-size attribute (only |
|Word, according to current operand size (e. g., |
|Word, according to current stack size (only |
|Doubleword, according to address-size attribute (only |
|Doubleword, according to current operand size (e. g., |
|Quadword, according to address-size attribute (only |
|Quadword, according to current stack size (only |
In this version, the reference is almost complete. It contains general, system, x87 FPU, MMX, SSE, SSE1, SSE2, SSE3, SSSE3, SSE4, VMX, and SMX instructions (both one-byte and two-byte ones). We are working on AMD-specific instructions and Intel AVX instructions now.
The MMX and SSE* instruction classification among groups is considered experimental and may change in future.
Note that from the point of project's progress, modifications of any of HTML editions is almost useless. A HTML edition is just a result of transformation of source XML file, so all modifications need to be done there.
Bukowski's disassembler is first public implementation of the XML reference.
Mediana, maintained by Mikae, is table-based x86/x86-64 disassembler engine. However, the transformation from source XML file is not a part of the project.
Since version 1.12, the reference is licensed under GPL-3.0. For more see its GitHub repository.
The old license (used up to version 1.12) is not available anymore.
This reference has been completed using the following resources:
Intel iAPX 86/88, 186/188 User's manual
Thanks to all these geeks involved in some way in this project:
Christian Ludloff: maintainer of Sandpile.org site, one of important sources for this project
Martin Mocko a.k.a. vid: many design ideas for HTML editions
Anthony Lopes: great XML and XSL contributions
Aquila: many great contributions
EliCZ: bug reports, design ideas
Cephexin: many great contributions to XML
Assembly Cheat Sheet Pdf
William Whistler: valuable reviews and bug reports
Mikae: reviews, bug reports
The source files can be downloaded from GitHub repository.
HTML Editions Files
My contact information is here.
X86 Register Cheat Sheet
(dates format correspond to ISO 8601)